View MC33596_4622448.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? freescale semiconductor, inc., 2006, 2007. all rights reserved. freescale semiconductor data sheet MC33596 rev. 3, 06/2007 1 overview the MC33596 is a highly integrated receiver designed for low-voltage applications. it includes a programmable pll for mult i-channel applications, an rssi circuit, a strobe oscillator that periodically wakes up the receiver whil e a data manager checks the content of incoming me ssages. a configuration switching feature allows automatic changing of the configuration between tw o programmable settings without the need of an mcu. 2features general: ? 304 mhz, 315 mhz, 426 mhz, 434 mhz, 868 mhz, and 915 mhz ism bands ? choice of temperature ranges: ? ?40c to +85c ? ?20c to +85c ? ook and fsk reception ? 20 kbps maximum data rate using manchester coding ? 2.1 v to 3.6 v or 5 v supply voltage ? programmable via spi ? 6 khz pll frequency step 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 rssiout vcc2rf rfin gndlna vcc2vco gnd switch vcc2in gndsubd strobe nc vccin gndio seb sclk mosi miso confb dataclk rssic gnddig xtalin xtal0ut vccinout vcc2out vccdig vccdig2 rbgap gnd nc gnd qfn32 lqfp32 gnd MC33596 pll tuned uhf receiver for data transfer applications
MC33596 data sheet, rev. 3 features freescale semiconductor 2 ? current consumption: ? 10.3 ma in rx mode ? less then 1 ma in rx mode with strobe ratio = 1/10 ? 260 na standby and 24 a off currents ? configuration switching ? allows fa st switching of two register banks receiver: ? ?106.5 dbm sensitivity, up to ?108 dbm in fsk 2.4 kbps ? digital and analog rssi (recei ved signal streng th indicator) ? automatic wakeup func tion (strobe oscillator) ? embedded data processor with programmable word recognition ? image cancelling mixer ? 380 khz if filter bandwidth ? fast wakeup time ordering information temperature range qfn package lqfp package ?40c to +85c MC33596fce/r2 MC33596fje/r2 ?20c to +85c MC33596fcae/r2 MC33596fjae/r2
features MC33596 data sheet, rev. 3 freescale semiconductor 3 figure 1. block diagram lin +i/q mixers pma + i/q image reject 1.5 mhz, bw 400 khz if amplifier detector analog data filter and slicer rx data manager spi fm-to-am converter agc fm_am agc_control data_rate gain_set agc_control rfin vcc2rf state machine switch_testout /2 or buffer /2 pfd xco clock generator vco vcc2vc0 gndlna band fractional divider if_ref_clock dig_clock band band voltage regulator analog test logarithmic amplifier rssi 4 bits a/d strobe oscillator v & i reference voltage regulator rssiout_testin switch_testout analog_signals test_control acclna rssi_8bits vccinout vcc2out vcc2in rbgap strobe mosi miso sclk seb rssic confb gnd gnd gnddig gndio gndsubd gndsuba dataclk xtalout xtalin vccdig vccdig2 band pre regulator vccin
MC33596 data sheet, rev. 3 pin functions freescale semiconductor 4 3 pin functions table 1. pin functions pin name description 1 rssiout rssi analog output 2 vcc2rf 2.1 v to 2.7 v internal supply for lna 3 rfin rf input 4 gndlna ground for lna (low noise amplifier) 5 vcc2vco 2.1 v to 2.7 v internal supply for vco 6 gnd ground 7 nc not connected 8 gnd ground 9 xtalin crystal oscillator input 10 xtalout crystal oscillator output 11 vccinout 2.1 v to 3.6 v power supply/regulator output 12 vcc2out 2.1 v to 2.7 v voltage regulator output for analog and rf modules 13 vccdig 2.1 v to 3.6 v power supply for voltage limiter 14 vccdig2 1.5 v voltage limiter output for digital module 15 rbgap reference voltage load resistance 16 gnd general ground 17 gnddig digital module ground 18 rssic rssi control input 19 dataclk data clock output to microcontroller 20 confb configuration mode selection input 21 miso digital interface i/o 22 mosi digital interface i/o 23 sclk digital interface clock i/o 24 seb digital interface enable input 25 gndio digital i/o ground 26 vccin 2.1 v to 3.6 v or 5.5 v input 27 nc no connection 28 strobe strobe oscillator capacit or or external control input 29 gndsubd ground 30 vcc2in 2.1 v to 2.7 v power supply for analog modules for decoupling capacitor 31 switch rf switch control output 32 gnd general ground
silicon version MC33596 data sheet, rev. 3 freescale semiconductor 5 4 silicon version this data sheet describes the functiona l features of silicon version es4.1. 5 maximum ratings table 2. maximum ratings parameter symbol value unit supply voltage on pin: vccin v ccin v gnd ?0.3 to 5.5 v supply voltage on pins: vccinout, vccdig v cc v gnd ?0.3 to 3.6 v supply voltage on pins: vcc2in, vcc2rf, vcc2vco v cc2 v gnd ?0.3 to 2.7 v voltage allowed on each pin (except digital pins) ? v gnd ?0.3 to v cc2 v voltage allowed on digital pins: seb, sclk, miso, mosi, confb, dataclk, rssic, strobe v ccio v gnd ?0.3 to v ccin +0.3 v esd hbm voltage capability on each pin 1 notes: 1 human body model, aec-q100-002 rev. c. ? 2000 v esd mm voltage capability on each pin 2 2 machine model, aec-q100-003 rev. c. ? 200 v solder heat resistance test (10 s) ? 260 c storage temperature t s ?65 to +150 c junction temperature t j 150 c
MC33596 data sheet, rev. 3 power supply freescale semiconductor 6 6power supply the circuit can be supplied from a 3 v voltage regulator or battery cel l by connecting vccin and vccinout. it is also possible to use a 5 v power supply connected to vccin; in this case vccinout should not be connected to vccin. an on-chip low drop-out voltage regulator supplie s the rf and analog modules (except the strobe oscillator and the low vo ltage detector, which are directly supplied from vccinout). this voltage regulator is supplied from pin vccinout and its output is connected to vcc2out. an external capacitor must be inserted betw een vcc2out and gnd for stabiliza tion and decoupling. the analog and rf modules must be supplied by vcc2 by exte rnally wiring vcc2out to vcc2in, vcc2rf and vcc2vco. figure 2. wiring diagrams a second voltage regulator s upplies the digital part. this regulator is powered from pin vccdig and its output is connected to vccdig2. an external cap acitor must be inserted between vccdig2 and table 3. supply voltage range versus ambient temperature parameter symbol temperature range 1 notes: 1 ?40c to +85c: MC33596fce/fje. ?20c to +85c: MC33596fcae/fjae. unit ?40c to +85c ?20c to +85c supply voltage on vccin, vccinout, vccdig for 3 v operation v cc3v 2.7 to 3.6 2.1 to 3.6 v supply voltage on vccin for 5 v operation v cc5v 4.5 to 5.5 4.5 to 5.5 v 3-v operation 5-v operation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 rssiout vcc2rf rfin gndlna v cc2vco gnd nc gnd gnd switch vcc2in gndsubd strobe nc vccin gndio seb sclk mosi miso confb dataclk rssic gnddig xtalin xtal0ut v ccnout vcc2out vccdig vccdig2 rbgap gnd vcc2 u15 MC33596 vcc2 3 v vcc2 vcc2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 rssiout vcc2rf rfin gndlna v cc2vco gnd nc gnd gnd switch vcc2in gndsubd strobe nc vccin gndio seb sclk mosi miso confb dataclk rssic gnddig xtalin xtal0ut v ccinout vcc2out vccdig vccdig2 rbgap gnd vcc2 u14 MC33596 vcc2 5 v vcc2 vcc2
supply voltage monitoring and reset MC33596 data sheet, rev. 3 freescale semiconductor 7 gnddig, for decoupling. the supply voltage vccdig2 is equal to 1.6 v. in standby mode, this voltage regulator goes into an ultra-low- power mode, but vccdig2 = 0.7 x v ccdig . this enables the internal registers to be supplied, allowing configuration data to be saved. 7 supply voltage monitoring and reset at power-on, an internal reset signal is generated. all registers are reset. when the lvde bit is set, the low-voltage detecti on module is enabled. this block compares the supply voltage on vccinout with a refere nce level of about 1.8 v. if the voltage on vccinout drops below 1.8 v, status bit lvds is set. the information in status bit lvds is latched and reset after a read access. note if lvde = 1, the lvd module remains enabled. the circuit cannot be put in standby mode, but rema ins in lvd mode with a higher quiescent current, due to the monitoring circuitry. l vd function is not accurate in standby mode. 8 receiver functional description the receiver is based on a superheterodyne architectur e with an intermediate frequency (if) of 1.5 mhz (see figure 1 ). its input is connect ed to the rfin pin. frequency dow n conversion is done by a high-side injection i/q mixer driven by the frequency synthesizer. an integrated poly-phase filter performs rejection of the image frequency. the low intermediate frequency allows integration of the if filter providing the selectivity. the center frequency is tuned by automatic frequency control (afc ) referenced to the crysta l oscillator frequency. sensitivity is met by an overall am plification of approximately 96 db, distributed over the reception chain, comprising low-noise amplif ier (lna), mixer, post-mixer amplifier, and if amplifier. automatic gain control (agc), on the lna and the if amplifier, maintains linearity and prevents internal saturation. sensitivity can be reduced using four programmable steps on the lna gain. amplitude demodulation is achieved by peak detection and comparison wi th a fixed or adaptive voltage reference selected during c onfiguration. frequency demodulation is ach ieved in two steps: the if amplifier agc is disabled and acts as an amplitude limiter; a filter performs a frequenc y-to-voltage conversion. the resulting signal is th en amplitude demodulated in the same wa y as in the case of amplitude modulation with an adaptive voltage reference. a low-pass filter improves the signal-to-noise ratio. shaped data are available if the in tegrated data manager is not used. if used, the data manager performs clock recovery a nd decoding of manchester c oded data. data and clock are then available on the se rial peripheral interface (spi). the c onfiguration sets the data rate range managed by the data manager and the bandwidth of the low-pass filter. an internal low-frequency oscillator can be used as a strobe oscillat or to perform an automatic wakeup sequence.
MC33596 data sheet, rev. 3 frequency planning freescale semiconductor 8 it is also possible to define two di fferent configurations for the receiver (frequency, da ta rate, data manager, modulation, etc.) that are automatically loaded during wakeup or under mcu control. if the pll goes out of lock, received data are ignored. 9 frequency planning 9.1 clock generator all clocks running in the circuit are derived from th e reference frequency provided by the crystal oscillator (frequency f ref , period t ref ). the crystal frequency is chosen in relation to the band in which the MC33596 has to operate. table 4 shows the value of the cf bits. 9.2 intermediate frequency the if filter is controlled by the crystal oscillator to guarantee the frequency over temperature and voltage range. the if filter center frequency, fif, can be computed using the crystal frequency f ref and the value of the cf bits: ? if cf[0] = 0 : fif = f ref /9*1.5/2 ? if cf[0] = 1 : fif = f ref /12*1.5/2 the cut-off frequency given in the parametric section can be computed by scaling to the fif. example 1. cut-off frequency computation compute the low cut-off frequency of the if fi lter for a 16.9683 mhz crystal oscillator. for this reference frequency, fif = 1.414 mhz. so, the 1.375 1 mhz low cut-off frequency specified for a 1.5 mhz if frequency becomes 1.375 1 *1.414/1.5 = 1.296 mhz table 4. crystal frequency and cf values versus frequency band rf frequency (mhz) cf1 cf0 lof1 lof0 f ref (crystal frequency) (mhz) f if (if frequency) (mhz) dataclk divider f dataclk (khz) digclk divider f digclk (khz) t digclk (s) 304 0 0 0 0 16.96745 1.414 60 282.791 30 565.582 1.77 315 0 0 1 0 17.58140 1.465 60 293.023 30 586.047 1.71 426 0 1 0 1 23.74913 1.484 80 296.864 40 593.728 1.68 433.92 0 1 0 1 24.19066 1.512 80 302.383 40 604.767 1.65 868.3 1 1 0 1 24.16139 1.510 80 302.017 40 604.035 1.66 916.5 1 1 1 1 25.50261 1.594 80 318.783 40 637.565 1.57 1. refer to parameter 3.3 found in section 18.1, ?general parameters . ?
register access through spi MC33596 data sheet, rev. 3 freescale semiconductor 9 9.3 frequency synthesizer description the frequency synthesizer consists of a local oscill ator (lo) driven by a fractional n phase locked loop (pll). the lo is an integrated lc voltage controlled osci llator (vco) operating at tw ice the rf frequency (for the 868 mhz frequency band) or four times the rf frequency (for the 434 mhz and 315 mhz frequency bands). this allows the i/q signals driv ing the mixer to be generated by division. the fractional divider offers high flexib ility in the frequency generation for: ? switching between transm it and receive modes. ? achieving frequency modulation in fsk modulation transmission. ? performing multi-channel links. ? trimming the rf carrier. frequencies are controlled by means of registers. to allow for user preference, two programming access methods are offered (see section 16.3, ?frequency register ?). ? in friendly access, all frequenc ies are computed internally fro m the contents of the carrier frequency and deviati on frequency registers. ? in direct access, the user programs di rect all three frequency registers. 10 register access through spi 10.1 spi interface the MC33596 and the mcu communicate via a bidirectiona l serial digital interface. according to the selected mode, the MC33596 or the mcu manages the data transfer. the MC33596?s digital interface can be used as a standard spi (master/slave) or as a simp le interface (spi deselected). in the latter case, the interface?s pins are used as standard i/o pins. however, the mcu has the highest priority, as it can control the MC33596 by setting confb pin to the low level. the interface is operated by four i/o pins. ? seb ? serial interface enable when seb is set high, pins sclk, mosi, and mi so are set to high impedance. this allows individual selection in a multiple device system, where all devices are connected via the same bus. the rest of the circuit remains in the current st ate, enabling fast recove ry times, but the power amplifier is disabled to preven t any uncontrolled rf transmission. ? sclk ? serial clock synchronizes data movement in and out of th e device through its mosi and miso lines. the master and slave devices can exchange a byte of information during a sequence of eight clock cycles. since sclk is generated by the master de vice, this line is an input on a slave device. ? mosi ? master output slave input transmits bytes when master, and receives bytes when slave, with the most significant bit first. when no data are output, sclk and mosi force a low level.
MC33596 data sheet, rev. 3 register access through spi freescale semiconductor 10 ? miso ? (master input) slave output transmits data when slave, with the msb first. there is no mast er function. data are valid on falling edges of sclk. this means that the clock phase and polarity control bits of the microcontroller spi have to be cpol = 0 and cpha = 1 (using freescale acronyms). table 5 summarizes the serial digital interf ace feature versus the selected mode. the data transfer protocol for each mode is described in the following sections. 10.2 configuration mode this mode is used to write or read the internal registers of the MC33596. as long as a low level is applied to confb (see figure 27 ), the mcu is the master node driving the sclk input, the mosi line input, and the miso line output. whatever the dire ction, spi transfers are 8-bit based and always begin with a command byte, which is suppl ied by the mcu on mosi. to be considered as a command byte, this byte must come after a falling edge on confb. figure 3 shows the content of the command byte. bits n[1:0] specify the number of accessed registers, as defined in table 6 . bits a[4:0] specify the address of the first register to access. this address is th en incremented internally by n after each data byte transfer. table 5. serial digital interface feature versus selected mode (seb = 1) selected mode MC33596 digital interface use configuration spi slave, data received on mosi, sclk from mcu, miso is output transmit spi deselected, mosi receives encoded data from mcu receive dme = 1 spi master, data sent on mosi with clock on sclk dme = 0 spi deselected, received data are directly sent to mosi standby / lvd spi deselected, all i/o are high impedance bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name n1 n0 a4 a3 a2 a1 a0 r/w figure 3. command byte table 6. number n of accessed registers n[1:0] number n of accessed registers 00 1 01 2 10 4 11 8
register access through spi MC33596 data sheet, rev. 3 freescale semiconductor 11 r/w specifies the type of operation: 0=read 1=write thus, this bit is associated with the presence of information on mosi (when writing) or miso (when reading). figure 4 and figure 5 show write and read operati ons in a typical spi transfer. in both cases, the spi is a slave. a received byte is considered internally on the eighth falli ng edge of sclk. cons equently, the last received bits, which do not form a complete byte, are lost. note a low level applied to confb does not affect the configuration register contents. figure 4. write operation in co nfiguration mode (n[1:0] = 01) figure 5. read operation in configuration mode (n[1:0] = 01) 10.3 configuration switching this feature allows for defining tw o different configurations using tw o different banks, and for switching them automatically during wakeup when using a strobe oscilla tor, or by means of the strobe pin actuation by the mcu. seb confb sclk (input) mosi (input) miso (output) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 n1 n0 a4 a3 a2 a1 a0 r/w seb confb sclk (input) mosi (input) miso (output) d7 d6 d5 d4 d3 d2 d1 d0 n1 n0 a4 a3 a2 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0
MC33596 data sheet, rev. 3 register access through spi freescale semiconductor 12 10.3.1 bit definition two sets of configurati on registers are available. they are gr ouped in two different banks: bank a and bank b. two bits are used to define which bank represents the state of the component. at any time, it is possible to know what is the active bank by reading the status bit banks. 10.3.2 bank access and register mapping registers are physically mapped foll owing a byte organization. the possibl e address space is 32 bytes. the base address is specified in the comm and byte. this is then incremented internally to address each register, up to the number of registers specifi ed by n[1:0], also specified by this command byte. all registers can then be scanned, whatever the type of transmission (read or write); howev er, writing to read-only bits or registers has no effect. when the last implemented address is reac hed, the internal address counter automatically loops back to th e first mapped address ($00). at any time, it is possible to write or read the content of any register of bank a a nd bank b. register access is defined as follows: r/w bit can be read and written. r bit can be read. write has no effect on bit value. rr bit can be read. read or write resets the value. r [a] bit can be read, this returns the same value as bank a. rr [a] bit can be read, this returns the same value as bank a. read or write resets the value. bit name direction location banka r/w bank a bankb r/w bank b banka bankb actions x 0 bank a is active 0 1 bank b is active 1 1 bank a and bank b are active and will be used one after the other bit name direction location comment banks r a & b bank status: indicates which register bank is active. this bit, available in bank a and bank b, returns the same value. table 7. access to specific bits bit bank byte access comment reset a config1 r/w available in banka. ols a, b config3 r-r[a] bit value is the real time status of the pll, banka, and bankb access reflect the same value. ldvs a, b config3 rr-rr[a} bit value is the latched value of the low-voltage detector. read or write from any bank resets value. soe a, b config2 r/w-r[a} soe can be modified in banka. access from bankb reflects banka value. rssix a, b rssi r-r[a} rssi value is dire ctly read from rssi converter. reflected value is the same whatever the active byte.
register access through spi MC33596 data sheet, rev. 3 freescale semiconductor 13 00h config1-a 91 h 0dh config1-b 91 h bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit name lof1 lof0 cf1 cf0 reset sl lvde clke bit name lof1 lof0 cf1 cf0 ? sl lvde clke reset value 1 0 0 1 0 0 0 1 reset value 1 0 0 1 0 0 0 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w 0 = 304?434 304?315 315?434 314 no t/r no no 0 = 304?434 304?315 315?434 314 ? t/r no no 1 = 315?916 434?916 868 434?868 yes r/t yes yes 1 = 315?916 434?916 868 434?868 ? r/t yes yes 01h config2-a 10 h 0eh config2-b 10 h bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit name dsref frm modu dr1 dr0 trxe dme soe bit name dsref frm modu dr1 dr0 trxe dme soe reset value 0 0 0 1 0 0 0 0 reset value 0 0 0 1 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r[a] 0 = fixed friendly ook 2.4?4.8 2.4?9.6 standby no no 0 = fixed friendly ook 2.4?4.8 2.4?9.6 standby no no 1 = adaptive direct fsk 9.6?19.2 4.8?19.2 enable yes yes 1 = adaptive direct fsk 9.6?19.2 4.8?19.2 enable yes yes 02h config3-a 30 h 0fh config3-b 30 h bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit name aff1 aff0 ols lvds ila1 ila0 ola1 ola0 bit name aff1 aff0 ols lvds ila1 ila0 ola1 ola0 reset value 0 0 1 1 0 0 0 0 reset value 0 0 1 1 0 0 0 0 r/w r/w r rr r/w r/w r/w r/w r/w r/w r[a] rr[a] r/w r/w r/w r/w 0 = 0.5?1 khz 0.5?2 khz ras ras 0?8 db 0?14 db 0?8 db 0?14 db 0 = 0.5?1 khz 0.5?2 khz ras ras 0?8 db 0?14 db 0?8 db 0?14 db 1 = 2?4 khz 1?4 khz unlocked low v 14?24 db 8?24 db 14?24 db 8?24 db 1 = 2?4 khz 1?4 khz unlocked low v 14?24 db 8?24 db 14?24 db 8?24 db 03h command-a 9 h 10h command-b 9 h bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit name affc ifla mode rssie edd ragc fagc banks bit name affc ifla mode rssie edd ragc fagc banks reset value 0 0 0 0 1 0 0 1 reset value 0 0 0 0 1 0 0 1 r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r[a] 0 = affx off no rx no slow dec. no no b bank 0 = affx off no rx no slow dec. no no b bank 1 = affx on ?20 db tx yes fast dec. yes yes a bank 1 = affx on ?20 db tx yes fast dec. yes yes a bank 04h f1-a 48 h 11h f1-b 4800 h bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit name fsk3 fsk2 fsk1 fsk0 f11 f10 f9 f8 bit name fsk3 fsk2 fsk1 fsk0 f11 f10 f9 f8 reset value 0 1 0 0 1 0 0 0 reset value 0 1 0 0 1 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 05h f2-a 0 h 12h f2-b 0 h bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit name f7 f6 f5 f4 f3 f1 f1 f0 bit name f7 f6 f5 f4 f3 f1 f1 f0 reset value 0 0 0 0 0 0 0 0 reset value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bank a registers bank b registers figure 6. bank registers
MC33596 data sheet, rev. 3 freescale semiconductor 14 register access through spi 06h ft1-a 700701 h 13h ft1-b 700701 h bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit name fta11 fta10 fta9 fta8 fta7 fta6 fta5 fta4 bit name fta11 fta10 fta9 fta8 fta7 fta6 fta5 fta4 reset value 0 1 1 1 0 0 0 0 reset value 0 1 1 1 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 07h ft2-a 7 h 14h ft2-b 7 h bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit name fta3 fta2 fta1 fta0 ftb11 ftb10 ftb9 ftb8 bit name fta3 fta2 fta1 fta0 ftb11 ftb10 ftb9 ftb8 reset value 0 0 0 0 0 1 1 1 reset value 0 0 0 0 0 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 08h ft3-a 1 h 15h ft3-b 1 h bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit name ftb7 ftb6 ftb5 ftb4 ftb3 ftb2 ftb1 ftb0 bit name ftb7 ftb6 ftb5 ftb4 ftb3 ftb2 ftb1 ftb0 reset value 0 0 0 0 0 0 0 1 reset value 0 0 0 0 0 0 0 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 09h rxonoff-a 75 h 16h rxonoff-b 75 h bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit name banka ron3 ron2 ron1 ron0 roff2 roff1 roff0 bit name bankb ron3 ron2 ron1 ron0 roff2 roff1 roff0 reset value 0 1 1 1 1 1 1 1 reset value 0 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0ah id-a c0 h 17h id-b c0 h bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit name idl1 idl0 id5 id4 id3 id2 id1 id0 bit name idl1 idl0 id5 id4 id3 id2 id1 id0 reset value 1 1 0 0 0 0 0 0 reset value 1 1 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0bh header-a 80 h 18h header-b 80 h bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit name hdl1 hdl0 hd5 hd4 hd3 hd2 hd1 hd0 bit name hdl1 hdl0 hd5 hd4 hd3 hd2 hd1 hd0 reset value 1 0 0 0 0 0 0 0 reset value 1 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0ch rssi-a 80 h 19h rssi-b 80 h bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 bit name rssi7 rssi6 rssi5 rssi4 rssi3 rssi2 rssi1 rssi0 b it name rssi7 rssi6 rssi5 r ssi4 rssi3 rssi2 rssi1 rssi0 reset value 0 0 0 0 0 0 0 0 reset value 0 0 0 0 0 0 0 0 rrrrrrrr r[a]r[a]r[a]r[a]r[a]r[a]r[a]r[a] bank a registers bank b registers figure 6. bank registers (continued)
register access through spi MC33596 data sheet, rev. 3 freescale semiconductor 15 10.3.3 direct switch control the conditions to enter direct switch control are: ? strobe pin = v cc ? soe bit = 0 by simply writing banka and bankb , the active bank will be defined: defined bank is active after exiting the c onfiguration mode, i.e., confb line goes high. the direct switch control should be used when: ? when the strobe oscillator cannot be used to de fine the switch timing (f or example, not periodic) ? when strobe pin use is not possible (no sl eep mode between the two configurations) ? no automatic switching is require d and mcu spi access is possible 10.3.4 strobe pin switch control the conditions to enter stro be pin switch control are: ? strobe pin: controlled by mcu i/o port ? soe bit = 0 by simply writing banka and bankb , the active banks will be defined. the strobe pin will control the off/on state of the MC33596. the various available sequences are described in the following subsections. 10.3.4.1 banka = x, bankb = 0 if strobe pin is 1, configurati on is defined by bank a, banks = 1 if strobe pin is 0, MC33596 configuration is off. if a message is received during state a, curren t state remains state a up to end of message. banka bankb x 0 bank a is active 0 1 bank b is active 1 1 not allowed in direct switch control banka bankb x 0 bank a is active 0 1 bank b is active 1 1 bank a and bank b are both active, configuration will toggle at each wakeup state a off state a off strobe pin
MC33596 data sheet, rev. 3 register access through spi freescale semiconductor 16 10.3.4.2 banka = 0, bankb = 1 if strobe pin is 1, configurati on is defined by bank b, banks = 0. if strobe pin is 0, MC33596 configuration is off. if a message is received during state b, curren t state remains state b up to end of message. 10.3.4.3 banka = 1, bank b = 1 if strobe pin is 1, configuration is defined by banks. banks is toggled at each falling edge of the strobe pin. if strobe pin is 0, MC33596 configuration is off. if a message is received during stat e a or state b, current state rema ins the same up to end of message. if a read or write access is done us ing spi, the next sequence will be gin with state a whatever was the active state before spi access by mcu. 10.3.5 strobe oscillator switch control the conditions to enter strobe oscillator switch control are: ? strobe pin connected to an extern al capacitor to define timing (see section 13, ?receiver on/off control? ) ? strobe pin can also be c onnected to the mcu i/o port ? soe bit = 1 by simply writing banka and bankb , the active banks will be defined. mcu can override strobe oscillator control by controlling strobe pin level. if mcu i/o port is in high impedance, strobe oscillator wi ll control the off/on state of the MC33596. the various available sequences are described in the following subsections. banka bankb x 0 bank a is active 0 1 bank b is active 1 1 bank a and bank b are both active, configuration will toggle at each wakeup off strobe pin state b off state b strobe pin banks bit state a off state b off state a
register access through spi MC33596 data sheet, rev. 3 freescale semiconductor 17 10.3.5.1 banka = x, bankb = 0 if strobe pin is 1, configurati on is defined by bank a, banks = 1. if strobe pin is 0, MC33596 configuration is off. if a message is received during state a, curren t state remains state a up to end of message. 10.3.5.2 banka = 0, bankb = 1 if strobe pin is 1, configurati on is defined by bank b, banks = 0. if strobe pin is 0, MC33596 configuration is off. if a message is received during state b, curren t state remains state b up to end of message. 10.3.5.3 banka = 1, bank b = 1 banks toggles at the end of each state a or state b. if strobe is forced to 1, configurat ion is frozen according to banks value. if a read or write access is done using spi, the next se quence will begin with stat e a in whatever was the active state before spi access by mcu. for all available sequences: ? state a and state b are defined by bank a and bank b. ? state a duration, tona is defined by bank a ron[3?0]. ? state b duration, tonb is defined by bank b ron[3?0]. ? off duration, tonb is defined by bank a roff[2?0]. ? if strobe pin is 1, the state is on and defined by banks at that time and remains this state up to the release of strobe and end of messa ge if a message is being received. ? if a message is being received during state a or b, current state remains state a or b up to end of message. state a off state a off state a off state b off state b state b banks bit state a state b off statea stateb off ab off a a a bbb off off strobe banks 1 z
MC33596 data sheet, rev. 3 communication protocol freescale semiconductor 18 ? if strobe pin is 0 the state is off. ? if strobe pin is released from 0 while stat e is off, the initial off period is completed. ? whenever is the change of duration of one stat e due to strobe pin level or a message being received, this has no influence on the timing of the following states (a, b, or off). 10.4 standby: lvd mode the spi is deselected. nothing is sent and all inco ming data are ignored until confb and seb go low to switch back to configuration mode. 11 communication protocol 11.1 manchester coding description the MC33596 data manager is able to decode manche ster coded messages. for other codings, the data manager should be disabled (dme=0) for raw data to be available on mosi. manchester coding is defined as foll ows: data is sent during the first half-bit; and the complement of the data is sent during the second half-bit. figure 7. example of manchester coding the signal average value is constant. this allows cloc k recovery from the data stream itself. to achieve correct clock recovery, manchest er coded data must have a du ty cycle between 47% and 53%. 11.2 preamble, identifier, header, and message the following description applies if the data manager is enabled (dme = 1). a complete telegram includes the fo llowing sequences: a preamble, an id entifier (id), the preamble again, a header, the message, and an end-of-message (eom). these bit sequences are described below. ? preamble: a preamble is required before th e id and before the header. it enables: ? in the case of ook modulation, the agc to set tle, and the data slicer reference voltage to settle if dsref = 1 ? in the case of fsk modulation, the data slicer reference voltage to settle ? clock recovery the preamble content must be defined carefully, to ensure that it will not be dec oded as the id or the header. figure 8 defines the preamble in ook and fsk modulation. 0 0 0 111 0 original manchester data coded data
communication protocol MC33596 data sheet, rev. 3 freescale semiconductor 19 ? id: the id allows selection of the correct device in an rf tran smission, as the content has been loaded previously in the id register. its lengt h is variable, defined by the idl[1:0] bits. the complement of the id is also recognized as the identifier. ? header: the header specifies the beginning of the message, as it is compared with the header register. its length is variable, de fined by the hdl[1:0] bits. the comp lement of the header is also recognized as the header, in this case, output data are complemented. ? the id and the header are sent at the same data rate as data. ? message: data must follow the header, with no delay. ? eom: the message is completed with an end- of-message, consisting of two consecutive nrz ones or zeroes (i.e., a manchester code violation). even in the case of fsk modulation, data must conclude with an eom, and not simply by stopping th e rf telegram. figure 9 shows a complete message comprising a 6-bit id and a 4-bit header, followed by two data bits. figure 8. preamble definition figure 9. complete message example notes: 1. the agc settling time pulse can be split over different pulses as long as the overall duration is at least 200 s. 2. ta b l e 1 4 defines the minimum number of manchester symbols r equired for the data slicer operation versus the data and average filters cut-off frequencies. 3. the manchester 0 symbol can be replaced by a 1. ook modulation (dsref = 0) agc settling time clock recovery id 1 manchester ?0? symbol ook modulation (dsref = 1) agc settling time data slicer refe rence settling time clock recovery id fsk modulation (dsref = 1) at least 3 manchester 0 symbols at data rate (2 and 3) data slicer reference se ttling time clock recovery at least 3 manchester 0 symbols at data rate (2 and 3) 1 manchester 0 symbol at data rate (3) 1 manchester 0 symbol at data rate (3) at data rate id 1 nrz > 200 s (1) 1 nrz > 200 s (1) preamble header data eom id preamble 110 011 0 0 0 11 1
MC33596 data sheet, rev. 3 communication protocol freescale semiconductor 20 note it is possible to build a tone to form the det ection sequence by programming the id register with a full sequence of ones or zeroes. in this case, the header (or its complement) must not be found in th is tone (i.e., it must not be a full sequence of ones or zeroes). 11.3 message protocol when the strobe oscillator is enab led (soe = 1), the receiv er is continuously on/of f cycling. the id must be recognized for the receiver to st ay on. consequently, the transmitted id burst must be long enough to include two consecutive receiver on cycles. when the strobe oscillator is not enabled (soe = 0), these timing constraints must be respected by the external control appl ied to pin strobe. figure 10. complete telegram with id detection figure 11. complete telegram with tone detection rf signal receiver status spi output p+id preamble id p+header preamble header p+id p+id p+id p+id p+id p+id == p+header data eom data on on time off off time id detected on off rf signal receiver status spi output header data eom data on on time off off time id detected on off tone
data manager MC33596 data sheet, rev. 3 freescale semiconductor 21 11.4 receiver startup delay as shown in figure 12 , a settling time is required when entering the on state. figure 12. receiver usable window 12 data manager in receive mode, manchester coded data can be processed internal ly by the data manager. after decoding, the data are output on the digital interface, in spi format. this minimizes the load on the mcu. the data manager, when enabled (dme = 1), has five purposes: ? id detection: the received identifier is compared with the identifier stored in the id register. ? header recognition: the received header is co mpared with the one stored in the header register. ? clock recovery: the clock is recovered during reception of the preamble and is computed from the shortest received pulse. during the reception of the telegram, th e recovered clock is constantly updated to the data rate of the incoming signal. ? output data and recovered clock on digital interface: see section 14.1, ?receive mode .? ? end-of-message detection: an eom consists of two consecutive nrz ones or zeroes. table 8 details some MC33596 featur es versus dme values. 13 receiver on/off control in receive mode, on/off sequencing can be controlled internally, or managed externally by the mcu through the input pin strobe. if the internal timer is selected (soe = 1), table 8. the MC33596 features versus dme dme digital interface use data format output 0 spi deselected bit stream no clock mosi ? 1 spi master when confb = 1 data bytes recovered clock mosi sclk receiver status rf signal off on off on settling time id detected id id id id id id id id
MC33596 data sheet, rev. 3 receiver on/off control freescale semiconductor 22 ? off time is clocked by the strobe oscillator, ? on time is clocked by the crystal oscillator, enabling accurate control of the on time and, therefore, the current consumption of the whole system. each time is defined with the associat ed value found in the rxonoff register. ? on time = ron[3:0] x 512 x t digclk (see table 17 ; begins after the crystal oscillator has started), ? off time = receiver off time = n x t strobe + min (t strobe / 2, receiver on time), with n decoded from roff[2:0] (see table 18 ). the strobe oscillator is a relaxation oscillator in which an external capacitor c3 is charged by an internal current source (see figure 43 ). when the threshold is reached, c3 is discharged and the cycle restarts. the strobe frequency is f strobe = 1/t strobe with t strobe =10 6 x c3. in receive mode, setting the strobe pin to v ccio at any time forces the circuit on. as v ccio is above the oscillator threshold voltage, the condi tion on which the strobe pin is set to v ccio is detected internally, and the oscillator pulldown circuitry is di sabled. this limits the current consumption. after a strobe forced at ?1?, the external driver should pass vi a a ?0? state to discharge the capacitor before going to high impedance state (otherwise, the on time w ould last a long time after the driver release). when the strobe oscillator is running (i.e., during an off time), forcing the strobe pin to v gnd stops the strobe clock and, therefore, maintains the circuit off. figure 13 shows the associated timings. figure 13. receiver on/off sequence strobe threshold strobe clock digital clock on counter receiver status off counter crystal oscillator startup cycling period off on off on 00 ron ron roff-1 roff t strobe strobe set to v ccio 00 ron
communication in receive mode MC33596 data sheet, rev. 3 freescale semiconductor 23 14 communication in receive mode 14.1 receive mode the MC33596 is master and drives th e digital interface in one of two ways, depending on the selection of the data manager. 1. dme = 1: the data manager is enabled. the spi is master. the MC33596 sends the recovered clock on sclk and the received data on the mosi line. data are valid on falling edges of sclk. if an entire number of bytes is received, the data manager may add an extra byte. the content of this extra byte is random. if the da ta received do not fill an entire number of bytes, the data manager will fill the last byte randomly. figure 14 shows a typical transfer. figure 14. typical transfer in receive mode with data manager 2. dme = 0: the data manager is disabled. the spi is deselected. raw data are sent directly on the mosi line, while sclk re mains at the low level. 15 received signal strength indicator (rssi) 15.1 module description in receive mode, a received si gnal strength indicator can be activated by setting bit rssie. the input signal is measured at tw o different points in the receiver chain by two different means, as follows. ? at the if filter output, a progre ssive compression logari thmic amplifier measur es the input signal, ranging from the sensitivity level up to ?50 dbm. ? at the lna output, the lna agc control voltage is used to monitor input signals in the range ?50 dbm to ?20 dbm. therefore, the logarithmic amplifie r provides information re lative to the in-band signal, whereas the lna agc voltage senses the i nput signal over a wider band. the rssi information given by the loga rithmic amplifier is available in: ? analog form on pin rssiout ? digital form in the four least signifi cant bits of the st atus register rssi seb sclk (output) mosi (output) recovered clock updated to incoming signal data rate d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0
MC33596 data sheet, rev. 3 received signal stre ngth indicator (rssi) freescale semiconductor 24 the information from the lna agc is available in digita l form in the four most significant bits of status register rssi. the whole content of status register rssi provides 2 x 4 bits of rssi information about the incoming signal (see section 16.6, ?rssi register ?). figure 15 shows a simplified block di agram of the rssi function. the quasi peak detector (d1, r1, c1 ) has a charge time of about 20 s to avoid sensitivity to spikes. r2 controls the decay time consta nt of about 5 ms to allow effici ent smoothing of the ook modulated signal at low data rates. this time constant is usef ul in continuous mode when s2 is permanently closed. to allow high-speed rssi updating in p eak pulse measurement, a discharge ci rcuit (s1) is required to reset the measured voltage and to allow new pe ak detection. figure 15. rssi simplified block diagram s2 is used to sample the rssi voltage to allow peak pulse measurement (s2 used as sample and hold), or to allow continuous transparent m easurement (s2 continuously closed). the 4-bit analog-to-digital convertor (adc) is base d on a flash architecture. the conversion time is 16xt diglck . as a single convertor is used for the two analog signals, the rssi register content is updated on a 32 x t digclk timebase. if rssie is reset, the whole rssi module is switched off, reducing the current consum ption. the output buffer connected to rssiout is set to high impedance. 15.2 operation two modes of operation are available: sample mode and continuous mode. 15.2.1 sample mode sample mode allows the peak pow er of a specific pulse in an incoming frame to be measured. the quasi peak detector is reset by closing s1. after 7 x t digclk , s1 is released. s2 is closed when rssic is set high. on the falling edge of rssic, s2 is opened. the voltage on rssi out is sampled and held. the last rssi conversion results are stored in the rssi register and no further conversion is done. rssiout adc rssi register msb lsb if filter output lna agc out s1 s2 r2 r1 c1 d1 c2
received signal strength indicator (rssi) MC33596 data sheet, rev. 3 freescale semiconductor 25 the rssi register is updated every 32 x t digclk . therefore, the minimum duration of the high pulse on rssic is 32 x t digclk . figure 16. rssi operation in sample mode closed 7 x t digclk updated frozen sampled and hold rssi voltage peak detector reset sampling open open frozen open closed closed rssic s1 s2 rssi register rssiout confb mosi miso cmd rssi value
MC33596 data sheet, rev. 3 configuration, command, and status registers freescale semiconductor 26 15.2.2 continuous mode continuous mode is used to make a peak measuremen t on an incoming frame, without having to select a specific pulse to be measured. the quasi peak detector is reset by closing s1. after 7 x t digclk , s1 is opened. s2 is closed when rssic is set high. as long as r ssic is kept high, s2 is cl osed, and rssiout follows th e peak value with a decay time constant of 5 ms. the adc runs continuously, and cont inually updates the rssi register. t hus, reading this register gives the most recent conversion value, pr ior to the register being read. th e minimum duration of the high pulse on confb is 32 x t digclk . figure 17. rssi operation in continuous mode 16 configuration, command, and status registers this section discusses the internal registers, which are composed of two classes of bits. ? configuration and command bits allow the MC33596 to operate in a suitable configuration. ? status bits report the current state of the system. all registers can be accessed by the spi ; these registers are described below. at power-on, the por resets all registers to a known va lue (in the shaded rows in the following tables). this defines the MC33596?s default configuration. after por, confb forces a low level. therefore, an external pullup resi stor is required to avoid entering configuration mode. 5 x t digclk peak detector test open frozen closed closed updated open frozen updated frozen rssic s1 s2 rssi register rssiout confb mosi miso cmd cmd rssi rssi
configuration, command, and status registers MC33596 data sheet, rev. 3 freescale semiconductor 27 16.1 configuration registers figure 18 describes configuratio n register 1, config1. reset is a global reset. the bit is cleared internally, after use. 0 = no action 1 = reset all registers and counters sl (switch level) selects the active level of the switch output pin. lvde (low voltage detection enable) en ables the low voltage detection function. 0 = disabled 1 = enabled note this bit is cleared by por. in the ev ent of a complete loss of the supply voltage, lvd is disabled at power-up, but the information is not lost as the status bit lvds is set by por. clke (clock enable) controls the dataclk output buffer. 0 = dataclk remains low 1 = dataclk outputs f dataclk bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr bit name lof1 lof0 cf1 c f0 reset sl lvde clke $00 reset value 1 0 0 1 0 0 0 1 figure 18. conf ig1 register table 9. lof[1:0] and cf[1:0] setting versus carrier frequency carrier frequency lof1 lof0 cf1 cf0 304 mhz 0000 315 mhz 1000 426 mhz 0101 434mhz 0101 868 mhz 0111 915 mhz 1111 table 10. active level of switch output pin sl receiver function level on switch 0 receiving low other high 1 other low receiving high
MC33596 data sheet, rev. 3 configuration, command, and status registers freescale semiconductor 28 figure 19 describes configuratio n register 2, config2. dsref (data slicer reference) se lects the data slicer reference. 0 = fixed reference (cannot be used in fsk) 1 = adaptive reference (recommended for maximum sensitivity in ook and fsk) in the case of fsk modulation (modu = 1), dsref must be set. frm (frequency register mana ger) enables either a user friendly a ccess to one frequency register or a direct access to the tw o frequency registers. 0 = the carrier frequency and the fsk deviation are defined by the f register 1 = the local oscillator frequency and the two carrier frequencies are defined by two frequency registers, f and ft. modu (modulation) sets th e data modulation type. 0 = on/off keying (ook) modulation 1 = frequency shift keying (fsk) modulation dr[1:0] (data rate) configure the re ceiver blocks operating in base band. ? low-pass data filter ? low-pass average filter generating the da ta slicer reference, if dsref is set ? data manager if the data manager is disabled, the incoming signal da ta rate must be lower th an or equal to the data manager maximum data rate. trxe (receiver enable) enables the whole receiver. 0 = standby mode 1 = other modes can be activated dme (data manager enable) enables the data manager. 0 = disabled 1 = enabled bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr bit name dsref frm modu dr1 dr0 trxe dme soe $01 reset value 0 0 0 1 0 0 0 0 figure 19. conf ig2 register table 11. base band parameter configuration dr1 dr0 data filter cut-off frequency average filter cut-off frequency data manager data rate range 0 0 6 khz 0.5 khz 2?2.8 kbd 0 1 12 khz 1 khz 4?5.6 kbd 1 0 24 khz 2 khz 8?10.6 kbd 1 1 48 khz 4 khz 16?22.4 kbd
configuration, command, and status registers MC33596 data sheet, rev. 3 freescale semiconductor 29 soe (strobe oscillator enable) enables the strobe oscillator. 0 = disabled 1 = enabled figure 20 describes configuratio n register 3, config3. ols (out of lock status) indicate s the current status of the pll. 0 = the pll is in lock-in range 1 = the pll is out of lock-in range lvds (low voltage detection status) indicates th at a low voltage event has occurred when lvde = 1. this bit is read-only and is cleared after a read access. 0 = no low voltage detected 1 = low voltage detected ila[1:0] (input level attenuation) de fine the rf input level attenuation. values in table 12 assume the lna gain is not reduced by the agc. aff[1:0] (average filter frequency) define the average filter cut-off frequency if the affc bit is set. if affc is reset, the average fi lter frequency is directly define d by bits dr[1:0], as shown in table 11 . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr bit name aff1 aff0 ols lvds ila1 ila0 - - $02 reset value 0 0 1 1 0 0 0 0 figure 20. conf ig3 register table 12. rf input level attenuation ila1 ila0 rf input level attenuation see parameter number 0 0 0 db 2.5 0 1 8 db 2.6 1 0 16 db 2.7 1 1 30 db 2.8 table 13. average filter cut-off frequency aff1 aff0 average filter cut-off frequency 0 0 0.5 khz 0 1 1 khz 1 0 2 khz 1 1 4 khz
MC33596 data sheet, rev. 3 configuration, command, and status registers freescale semiconductor 30 if affc is set, aff[1:0] allow the overall receiver sensitivity to be improved by reducing the average filter cut-off frequency. th e typical preamble duration of three manc hester zeroes or ones at the data rate must then be increased, as shown in table 14 . 16.2 command register figure 21 describes the comma nd register, command. affc (average filter frequency cont rol) enables direct control of th e average filter cut-off frequency. 0 = average filter cut-off frequency is defined by dr[1:0] 1 = average filter cut-off fre quency is defined by aff[1:0] ifla (if level attenuation) cont rols the maximum gain of the if amplifier in ook modulation. 0 = no effect 1 = decreases by 20 db (typical) the maximum gain of the if amplifier, in ook modulation only the reduction in gain can be obser ved if the if amplifier agc system is disabled (by setting ragc = 1). rssie (rssi enable) enables the rssi function. 0 = disabled 1 = enabled edd (envelop detector decay) cont rols the envelop detector decay. 0 = slow decay for minimum ripple 1 = fast decay ragc (reset automatic gain control) resets both receiver internal agcs. 0 = no action 1 = sets the gain to its maximum value table 14. minimum number of manchester symbols in preamble versus dr[1:0] and aff[1:0] dr[1:0] 00 01 10 11 aff[1:0] 00 361224 01 ?3 612 10 ?? 3 6 11 ??? 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr bit name affc ifla ? rssie edd ragc fagc ? $03 reset value 0 0 0 0 1 0 0 1 figure 21. command register
configuration, command, and status registers MC33596 data sheet, rev. 3 freescale semiconductor 31 a first spi access allows ragc to be set; a second spi access is required to reset it. fagc (freeze automatic gain control) freezes bot h receiver agc levels. 0 = no action 1 = holds the gain at its current value 16.3 frequency register figure 22 defines the frequency register, f. how this register is used is determined by the frm bit, which is described below. frm = 0 (user friendly access) bits f[11:0] define the carrier frequency f carrier . the local oscillator frequency f lo is then set automatically to f carrier + f if (with f if = intermediate frequency). frm = 1 (direct access) f[11:0] defines the receiver local oscillator frequency f lo table 15 defines the value to be binary coded in the frequency registers f[11;0 ], versus the desired frequency value f (in hz). conversely, table 16 gives the desired frequency f and the fre quency resolution versus the value of the frequency registers f[11;0]. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 addr bit name????f11f10f9f8$04 reset value 0 1 0 0 1 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name f7 f6 f5 f4 f3 f2 f1 f0 $05 reset value 0 0 0 0 0 0 0 0 figure 22. f register table 15. frequency register value versus frequency value f cf[1:0] frequency register value 00, 01 (2 x f/f ref -35) x 2048 11 (f/f ref -35) x 2048 table 16. frequency value f versus frequency register value cf[1:0] frequency (hz) fr equency resolution (hz) 00, 01 (35 + f[11;0]/2048)xf ref /2 f ref /4096 11 (35 + f[11;0]/2048)xf ref f ref /2048
MC33596 data sheet, rev. 3 configuration, command, and status registers freescale semiconductor 32 16.4 receiver on/off duration register figure 23 describes the receiver on/of f duration register, rxonoff. ron[3:0] (receiver on) define the r eceiver on time (after crystal oscill ator startup) as described in section 13, ?receiver on/off control .? roff[2:0] (receiver off) define the receiver off time as described in section 13, ?receiver on/off control .? 16.5 id and header registers figure 24 defines the id register, id. idl[1:0] (identifier lengt h) sets the length of the identifier, as shown on table 19 . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr bit name ? ron3 ron2 ron1 ron0 roff2 roff1 roff0 $09 reset value 0 1 1 1 1 1 1 1 figure 23. rxonoff register table 17. receiver on time definition ron[3:0] receiver on time: n x 512 x t digclk 0000 forbidden value 0001 1 0010 2 ... ... 1111 15 table 18. receiver off time definition roff[2:0] receiver off time: n x t strobe 000 1 001 2 010 4 011 8 100 12 101 16 110 32 111 63 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr bit name idl1 idl0 id5 id4 id3 id2 id1 id0 $0a reset value 1 1 0 0 0 0 0 0 figure 24. id register
configuration, command, and status registers MC33596 data sheet, rev. 3 freescale semiconductor 33 id[5:0] (identifier) sets the identifier. the id is ma nchester coded. its lsb corresponds to the register?s lsb, whatever the specified length. figure 25 defines the header register, header. hdl[1:0] (header length) sets the length of the header, as shown on table 20 . hd[5:0] (header) sets the header. the header is manc hester coded. its lsb corres ponds to the register?s lsb, whatever the specified length. 16.6 rssi register figure 26 describes the rssi re sult register, rssi. bits rssi[7:4] contain the result of the analog-to-digital conversion of the signal measured at the lna output. bits rssi[3:0] contain the result of the analog-to-digital conversion of the signal measured at the if filter output. table 19. id length selection idl1 idl0 id length 00 2 bits 01 4 bits 10 5 bits 1 1 6 bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr bit name hdl1 hdl0 hd5 hd4 hd3 hd2 hd1 hd0 $0b reset value 1 0 0 0 0 0 0 0 figure 25. header register table 20. header length selection hdl1 hdl0 hd length 0 0 1 bits 0 1 2 bits 1 0 4 bits 1 1 6 bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr bit name rssi7 rssi6 rssi5 r ssi4 rssi3 rssi2 rssi1 rssi0 $0c reset value 0 0 0 0 0 0 0 0 figure 26. rssi register
MC33596 data sheet, rev. 3 controller freescale semiconductor 34 17 controller this section describes how the mc 33596 controller executes sequences of operations, relative to the selected mode. the controller is a finite state machine, clocked at t digclk . an overview is presented in figure 27 (note that some branches refer to other diag rams that provide more detailed information). there are three different modes: c onfiguration, receive, and standby/lvd. each mode is exclusive and can be entered in different ways, as follows. ? external signal: confb for configuration mode, ? external signal and confi guration bits: confb and trxe for all other modes, ? external signal and in ternal conditions: see figure 31 and figure 33 for information on how to enter standby/lvd mode. after a por, the circui t is in state 60 (see figure 27 ) and configuration registers? content is set to the reset value. at any time, a low level appl ied to confb forces the finite state m achine into state 1, whatever the current state. this is not always shown in state diagrams, but must always be considered. figure 27. state machine overview 17.1 configuration mode the configuration mode is selected by the microcontroller unit (mcu) to write to the internal registers (to configure the system) or to read them. in this mode, the spi is a slave. the analog parts (receiver) remain in the state (on, off) they were in prior to entering configuration mode , until a new configuration changes them. in configuration mode, data can be neither sent nor received. as long as a low level is applied to confb, the circuit stays in stat e 1, the only state in this mode. figure 28 and figure 29 describe the two valid sequences fo r enabling a correct transition from standby/lvd mode to configuration mode. see figure 30 see figure 32 see figure 33 see figure 31 spi deselected spi slave spi master confb = 0 standby/lvd mode state 60 state 1 configuration mode configuration mode receive mode power-on reset confb = 1, trxe = 0, and strobe = 0 confb = 1, trxe = 1, and strobe = 0 and dme = 0 and dme = 1 and soe = 1 and soe = 1 and soe = 0 and soe = 0 active bank change (a to b or b to a)
controller MC33596 data sheet, rev. 3 freescale semiconductor 35 figure 28. first valid sequence from st andby/lvd mode to configuration mode figure 29. second valid sequence from standby/lvd mode to configuration mode 17.2 receive mode the receiver is either waiti ng for an rf telegram, or is receiving one. four different processes are possible, as determined by the va lues of the dme and soe bits. a stat e diagram describes the sequence of operations in each case. note if the strobe pin is tied to a high le vel before switching to receive mode, the receiver does not go thro ugh an off or standby state. 17.2.1 data manager disabled and strobe oscillator enabled raw received data are sent directly on the mosi line. figure 30 shows the state diagram. figure 30. receive mode, dme = 0, soie = 1 state 0: the receiver is off, but the strobe oscillator and the off c ounter are running. forcing the strobe pin low maintains the system in this state. strobe confb seb spi startup time strobe confb seb spi startup time 10 s (maximum) strobe = 0 strobe = 1 strobe = 0 spi deselected off counter = roff[2:0] or strobe = 1 on counter = ron[3:0] and strobe 1 state 0 off state 0b on raw data on mosi
MC33596 data sheet, rev. 3 controller freescale semiconductor 36 state 0b: the receiver is kept on by the strobe pin or the on c ounter. raw data are output on the mosi line. for all states: at any time, a low level applied to confb forces the state machine to state 1. 17.2.2 data manager disabled and strobe pin control raw received data are sent directly on the mosi line. figure 31 shows the state diagram. figure 31. receive mode, dme = 0, soe = 0 state 5: the receiver is in standby/ lvd mode. for further information, see section 17.3, ?standby/lvd mode .? a high level applied to strobe forces the circuit to state 5b. state 5b: the receiver is kept on by the stro be pin. raw data are out put on the mosi line. for all states: at any time, a low level applied to confb forces the state machine to state 1. 17.2.3 data manager enabled and strobe oscillator enabled figure 32 shows the state diagram when the data manager and the strobe oscillator are enabled. in this configuration, the receiver is controll ed internally by the strobe oscillato r. however, external control via the strobe pin is still possible, and ove rrides the strobe oscillator command. state 10: the receiver is off, but the strobe osci llator and the off counter are running. forcing strobe pin to the low level maintains the system in this state. state 11: the receiver is wa iting for a valid id. if an id, or its complement, is detected, the state machine advances to state 12; otherwise, the circuit goes ba ck to state 10 at the end of the ron time, if strobe 1. state 12: an id or its complement has been detected. the da ta manager is now waiting for a header or its complement. if neither a header, nor its complement, has been received before a time-out of 256 bits at data rate, the system returns to state 10. state 13: a header, or its complement, has been rece ived. data and clock signals are output on the spi port until eom indicates the end of the data sequence. if the complement of the header has been received, output data are complemented also. strobe = 0 strobe = 1 spi deselected strobe = 1 state 5 standby/lvd state 5b on raw data on mosi strobe = 0
controller MC33596 data sheet, rev. 3 freescale semiconductor 37 when an eom occurs before the current byte is fully shifted out, dummy bits ar e inserted until the number of shifted bits is a multiple of 8. for all states: at any time, a low le vel applied to strobe forces the ci rcuit to state 10, and a low level applied on confb forces the state machine to state 1. figure 32. receive mode, dme = 1, soe = 1 spi master strobe = 0 strobe = 0 strobe = 1 off counter = roff[2:0] or strobe = 1 on counter = ron[3:0] and strobe 1 time out header received eom received and strobe = 1 eom received and strobe 1 id detected state 10 off state 11 on waiting for a valid id state 12 on waiting for a valid header state 13 on output data and clock waiting for end of message
MC33596 data sheet, rev. 3 controller freescale semiconductor 38 17.2.4 data manager enabled and strobe pin control figure 33 shows the state diagram when the data manager is enabled a nd the strobe oscillator is disabled. in this configuration, the receiver is controlled only externally by the mcu. figure 33. receive mode, dme = 1, soe = 0 state 20: the receiver is in standby/lv d mode. for further information, see section 17.3, ?standby/lvd mode .? a high level applied to strobe forces the circuit to state 21. state 21: the circuit is wait ing for a valid id. if an id, or its complement, is detected, the state machine advances to state 22; if not, the state machine will remain in stat e 21, as long as strobe is high. state 22: if a header, or its complement, is detected, the state machine advan ces to state 23. if not, the state machine will remain in state 22, as long as strobe is high. state 23: a header or its complement has been received; data and cloc k signals are output on the spi port until an eom indicates the end of th e data sequence. if the complement of the header has been received, spi deselected strobe = 0 strobe = 1 header received eom received and strobe = 1 eom received and strobe = 0 id detected state 20 standby/lvd state 21 on waiting for a valid id state 22 on waiting for a valid header state 23 on output data and clock waiting for end of message spi master strobe = 0 strobe = 0 strobe = 1
controller MC33596 data sheet, rev. 3 freescale semiconductor 39 output data are complemented also. when an eom oc curs before the current byte is fully shifted out, dummy bits are inserted until the number of shifted bits is a multiple of 8. for all states: at any time, a low level applied to strobe puts the ci rcuit into state 20, and a low level applied to confb forces th e state machine to state 1. 17.3 standby/lvd mode standby/lvd mode allows minimum current consumpt ion to be achieved. depe nding upon the value of the lvde bit, the circuit is in standby mode (state 60) or lvd mode (state 5 and 20). lvde = 0: the receiver is in standby; consumption is reduced to leakage current (cur rent state after por). lvde = 1: the lvd function is enabled; consumpt ion is in the range of tens of microamperes. the only way to exit this mode is to go back to configuration mode by applying a low level to confb. 17.4 transition time table 21 details the different times that must be considered for a given tr ansition in the state machine, once the logic conditions for that transition are met. table 21. transition time definition transition state x -> y crystal oscillator startup time, parameter 5.10 pll timing receiver preamble time 1 notes: 1 see section 11.2, ?preamble, identifier, header, and message .? receiver on-to-off time, parameter 1.12 standby to spi running, state 60 -> 1 standby to receiver running, states 5 -> 5b, 20 -> 21 lock time parameter 5.9 off to receiver running, states 0 -> 0b, 10 -> 11 lock time parameter 5.9 configuration to receiver running, states 1 -> (0b, 5b, 11, 21) 0 or lock time parameter 5.1 or lock time parameter 5.9 2 2 depending on the pll status before entering configuration mode. for example, the transition time from standby to receiver running (fsk modulation, 19.2 kbd, affc = 0, data mana ger enabled) is: 0.6 ms + 50 s + (3 + 1)/19.2k = 970 s. receiver running to configuration mode, state (0b, 5b, 11, 12, 13, 21, 22, 23) -> 1, receiver running to standby mode, state 5b -> 5, (21, 22, 23) -> 20 receiver running to off mode, state 0b -> 0, (11, 12, 13) -> 10
MC33596 data sheet, rev. 3 electrical characteristics freescale semiconductor 40 18 electrical characteristics 18.1 general parameters 18.2 receiver: rf parameters rf parameters assume a matching network between test equipment and the d.u.t, and apply to all bands unless otherwise specified. operating supply voltage and temperature range see ta b l e 3 . values refer to the circuit recommended in the application schematic (see figure 43 ), unless otherwise specified. typical va lues reflect average measurement at v cc = 3.0 v, t a = 25 c. parameter test conditions comments limits unit min typ max 1.2 supply current in receive mode receiver on ? 10.3 13 ma 1.3 strobe oscillator only ? 24 50 a 1.6 supply current in standby mode ?40 c t a 25 c ? 260 700 na 1.8 t a = 85 c ? 800 1200 na 1.9 supply current in lvd mode lvde = 1 ? 35 50 a 1.12 receiver on-to-off time supply current reduced to 10% ? 100 ? s 1.13 vcc2 voltage regulator output 2.7 v < v cc 2.4 2.6 2.8 v 1.14 2.1 v v cc 2.7 v ? v cc ?0.1 ? v 1.15 vccdig2 voltage regulator output circuit in standby mode (v ccdig = 3 v) ? 0.7 x v ccdig ?v 1.16 circuit in all other modes 1.4 1.6 1.8 v 1.19 voltage on vcc (preregulator output) receive mode with vccin=5v 2.4 ? ? v operating supply voltage and temperature range see ta b l e 3 . values refer to the circuit recommended in the application schematic (see figure 43 ), unless otherwise specified. typical values reflect average measurement at v cc = 3.0 v, t a =25 c. parameter test conditions, comments limits unit min typ max (fce, fje) max (fcae, fjae) 2.2 ook sensitivity at 315 mhz dme = 1, dsref = 1, dr = 4.8 kbps, per = 0.1 ? ?104 ?99 ?97 dbm 2.40 ook sensitivity at 434 mhz dme = 1, dsref = 1, dr = 4.8 kbps, per = 0.1 ? ?103.5 ?98 ?96 dbm 2.41 ook sensitivity at 868 mhz dme = 1, dsref = 1, dr = 4.8 kbps, per = 0.1 ? ?103 ?98 ?96 dbm 2.42 ook sensitivity at 916 mhz dme = 1, dsref = 1, dr = 4.8 kbps, per = 0.1 ? ?103 ?98 ?96 dbm
electrical characteristics MC33596 data sheet, rev. 3 freescale semiconductor 41 2.24 fsk sensitivity at 315 mhz dme = 1, dsref = 1, dr = 4.8 kbps, df carrier = 64 khz, per = 0.1 ? ?106.5 ?102 ?100 dbm 2.50 fsk sensitivity at 434 mhz dme = 1, dsref = 1, dr = 4.8 kbps, df carrier = 64 khz, per = 0.1 ? ?105.5 ?101 ?99 dbm 2.51 fsk sensitivity at 868 mhz dme = 1, dsref = 1, dr = 4.8 kbps, df carrier = 64 khz, per = 0.1 ? ?104.5 ?100 ?98 dbm 2.52 fsk sensitivity at 916 mhz dme = 1, dsref = 1, dr = 4.8 kbps, df carrier = 64 khz, per = 0.1 ? ?105.4 ?102 ?100 dbm 2.35 sensitivity improvement in raw mode dme = 0 ? 0.6 ? ? db 2.5 sensitivity reduction ila[1:0] = 00 ? 0 ? ? db 2.6 ila[1:0] = 01 ? 8 ? ? db 2.7 ila[1:0] = 10 ? 16 ? ? db 2.8 ila[1:0] = 11 ? 30 ? ? db 2.9 in-band jammer desensitization sensitivity reduced by 3 db cw jammer at f carrier 50 khz/ook ??4??dbc 2.60 sensitivity reduced by 3 db cw jammer at f carrier 50 khz/fsk ??6??dbc 2.11 out-of-band jammer desensitization sensitivity reduced by 3db cw jammer at f carrier 1mhz ?37??dbc 2.12 sensitivity reduced by 3db cw jammer at f carrier 2mhz ?40??dbc 2.13 rfin parallel resistance receive mode ? 300 ? ? 2.14 rfin parallel resistance standby mode 1300 ? ? ? 2.15 rfin parallel capacitance receive mode ? 1.2 ? ? pf 2.17 maximum detectable signal, ook modulation depth: 99%, level measured on a nrz ?1? ?25 ? ? ? dbm 2.25 maximum detectable signal, fsk f carrier = 64khz -10 ? ? ? dbm 2.18 image frequency rejection 304?434 mhz 20 36 ? ? db 2.19 868?915 mhz 15 20 ? ? db operating supply voltage and temperature range see ta b l e 3 . values refer to the circuit recommended in the application schematic (see figure 43 ), unless otherwise specified. typical values reflect average measurement at v cc = 3.0 v, t a =25 c. parameter test conditions, comments limits unit min typ max (fce, fje) max (fcae, fjae)
MC33596 data sheet, rev. 3 electrical characteristics freescale semiconductor 42 figure 34. ook sensitivity variation versus temperature figure 35. ook sensitivity variation versus voltage ook sensitivity variation vs temperature (ref : 3v, 25c, 4800bps) -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -40c 25c 85c temperature (c) sensitivity variation (db) 315 mhz 434 mhz 868 mhz 916 mhz ook sensitivity variation vs voltage (ref : 3v, 25c, 4800bps) -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 2.1 v 2.4 v 3 v 3.6 v voltage (v) sensitivity variation (db) 315 mhz 434 mhz 868 mhz 916 mhz
electrical characteristics MC33596 data sheet, rev. 3 freescale semiconductor 43 figure 36. fsk sensitivity variation versus temperature figure 37. fsk sensitivity variation versus voltage fsk sensitivity variation vs temperature (ref : 3v, 25c, +/-64khz, 4800 bps ) -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -40c 25c 85c temperature (c) sensitivity variation (db ) 315 mhz 434 mhz 868 mhz 916 mhz fsk sensitivity variation vs voltage (ref : 3v, 25c, +/-64khz, 4800bps ) -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 2.1 v 2.4 v 3 v 3.6 v voltage (v) sensitivity variaition (db) 315 mhz 434 mhz 868 mhz 916 mhz
MC33596 data sheet, rev. 3 electrical characteristics freescale semiconductor 44 figure 38. ook sensitivity variation versus data rate figure 39. fsk sensitivity variation versus data rate sensitivity variation versus data rate (ref : 25c, 3v, 434mhz , ook, 4800bps) -3 -2 -1 0 1 2 3 4 5 2400 4800 9600 19200 data rate (bps) sensitivity variation (db) sensitivity variation vs data rate (ref : 25c, 3v, 434mhz , fsk +/-64khz, 4800bps) -3 -2 -1 0 1 2 3 4 5 2400 4800 9600 19200 data rate (bps) sensitivity variation (db)
electrical characteristics MC33596 data sheet, rev. 3 freescale semiconductor 45 figure 40. fsk sensitivity variation versus frequency deviation 18.3 receiver parameters operating supply voltage and temperature range see ta bl e 3 . values refer to the circuit recommended in the application schematic (see figure 43 ), unless otherwise specified. typical va lues reflect average measurement at v cc = 3.0 v, t a = 25 c. parameter test conditions comments limits unit min typ max receiver: if filter, if amplifier, f m-to-am converter and envelope detector 3.1 if center frequency refer to section 9, ?frequency planning? . ?1.5?mhz 3.2 if bandwidth at ?3db ? 380 ? khz 3.3 if cut-off low frequency at ?3 db ? ? 1.387 mhz 3.4 if cut-off high frequency at ?3 db 1.635 ? ? mhz 3.12 recovery time from strong signal ook modulation, 2.4 kbps, fagc = 0, input signal from ?50 dbm to ?100 dbm ?15?ms sensitivity variation vs frequency deviation (ref : 25c, 3v, 434mhz, fsk +/-64khz, 4800bps) -1 0 1 2 3 4 5 6 20 32 40 50 65 70 80 90 100 110 120 130 140 150 160 170 frequency deviation (khz) sensitivity variation (db)
MC33596 data sheet, rev. 3 electrical characteristics freescale semiconductor 46 18.4 pll & crystal oscillator receiver: analog and digital rssi 3.51 analog rssi output signal for input signal @?108 dbm measured on rssiout 380 ? 650 mv 3.52 analog rssi output signal for input signal @?100 dbm 420 ? 700 mv 3.53 analog rssi output signal for input signal @?70 dbm 850 ? 1200 mv 3.54 analog rssi output signal for input signal @?28 dbm 1000 ? 1300 mv 3.55 digital rssi registers for input signal @?108 dbm rssi [0:3] 0 ? 2 3.56 digital rssi registers for input signal @?100 dbm 0?3 3.57 digital rssi registers for input signal @?70 dbm 9?13 3.58 digital rssi registers for input signal @?28 dbm 13 ? 16 3.59 digital rssi registers for input signal @?70 dbm rssi [4:7] 0 ? 2 3.6 digital rssi registers for input signal @?50 dbm 4?8 3.61 digital rssi registers for input signal @?24 dbm 13 ? 15 operating supply voltage and temperature range see ta b l e 3 . values refer to the circuit recommended in the application schematic (see figure 43 ), unless otherwise specified. typical va lues reflect average measurement at v cc = 3.0 v, t a =25 c. parameter test conditions comments limits unit min typ max 5.9 pll lock time rf frequency 25khz ? 50 100 s 5.1 toggle time between 2 frequencies rf frequency step <1.5mhz, rf frequency 25khz ?30? s 5.10 crystal oscillator startup time ? 0.6 1.2 ms 5.8 crystal series resistance ? ? 120 operating supply voltage and temperature range see ta bl e 3 . values refer to the circuit recommended in the application schematic (see figure 43 ), unless otherwise specified. typical va lues reflect average measurement at v cc = 3.0 v, t a = 25 c. parameter test conditions comments limits unit min typ max
electrical characteristics MC33596 data sheet, rev. 3 freescale semiconductor 47 18.5 strobe oscillator (soe = 1) 18.6 digital input: confb, mosi, sclk, seb, strobe, rssic operating supply voltage and temperature range see ta b l e 3 . values refer to the circuit recommended in the application schematic (see figure 43 ), unless otherwise specified. typical va lues reflect average measurement at v cc = 3.0 v, t a =25 c. parameter test conditions comments limits unit min typ max 6.1 period range t strobe =10 6 .c3 0.1 ? ? ms 6.2 external capacitor c3 0.1 ? 10 nf 6.3 sourced/sink current wi th 1% resistor r13 ? 1 ? a 6.4 high threshold voltage ? 1 ? v 6.5 low threshold voltage ? 0.5 ? v 6.6 overall timing accuracy with 1% resistor r13 & 5% capacitor c3, 3 sigma variations ?14.2 ? 15.8 % operating supply voltage and temperature range see ta b l e 3 . values refer to the circuit recommended in the application schematic (see figure 43 ), unless otherwise specified. typical va lues reflect average measurement at v cc = 3.0 v, t a =25 c. parameter test conditions comments limits unit min typ max 7.7 input low voltage mosi , sclk , seb , rssic (1) notes: 1 input levels of those pins are referenced to v cc2 which depends upon v cc (see section 6, ?power supply ?). ? ? 0.4 x v cc2 v 7.8 input high voltage 0.8 x v cc2 ??v 7.9 input hysteresis 0.1 x v cc2 ??v 7.10 input low voltage confb , strobe 2 2 input levels of those pins are referenced to v ccdig2 which depends upon the circuit state (see section 6, ?power supply ?). ? ? 0.4 x v ccdig2 v 7.11 input high voltage 0.8 x v ccdig2 ??v 7.12 input hysteresis 0.1 x v ccdig2 ??v 7.5 sink current configuration, receive, modes 1 ? 100 na 7.6 standby or lvd modes 0.5 ? 10 na
MC33596 data sheet, rev. 3 electrical characteristics freescale semiconductor 48 18.7 digital output 18.8 digital interface timing operating supply voltage and temperature range see ta b l e 3 . values refer to the circuit recommended in the application schematic (see figure 43 ), unless otherwise specified. typical va lues reflect average measurement at v cc = 3.0 v, t a =25 c. parameter test conditions comments limits unit min typ max digital output: dataclk, lvd, miso, mosi, sclk 8.1 output low voltage | iload| =50 a ? ? 0.2 x v ccio v 8.2 output high voltage 0.8 x v ccio ??v 8.3 fall and rise time from 10% to 90% of the output swing, c load = 10pf ?80150ns digital output: switch (v cc = 3v) 8.4 output low voltage | iload| =50 a ? ? 0.2 x v cc v 8.5 output high voltage 0.8 x v cc ??v operating supply voltage and temperature range see ta b l e 3 . values refer to the circuit recommended in the application schematic (see figure 43 ), unless otherwise specified. typical va lues reflect average measurement at v cc = 3.0 v, t a =25 c. parameter test conditions comments limits unit min typ max 9.2 sclk period 1 ? ? s 9.8 configuration enable time 20 ? ? s 9.3 enable lead time if crystal oscillator is running, if not see page 15 for entering into configuration 3 x t digclk ??ns 9.4 enable lag time 100 ? ? ns 9.5 sequential transfer delay 100 ? ? 1 notes: 1 the digital interface can be used in spi burst protocol, i.e., with a continuous clock on sclk port. for example, one (or more) read access followed by one (or more) writ e access and so on. in this case and for a practical use, the pulse required on confb between accesses must be less than one digital clock period t digclk . ns 9.6 data hold time receive mode, dme = 1, from sclk to mosi 3 x t digclk ??s 9.7 data setup time configuration mode, from sclk to miso ??100ns 9.9 configuration mode, from sclk to mosi 120 ? ? ns 9.10 data setup time configuration mode, from sclk to mosi 100 ? ? ns
electrical characteristics MC33596 data sheet, rev. 3 freescale semiconductor 49 figure 41. digital interface timing diagram in configuration mode figure 42. digital interface timing diagram in receive mode (dme = 1) examples of crystal char acteristics are given in table 22 . table 22. typical crystal reference and characteristics parameter reference & type unit 315 mhz 434 mhz 868 mhz ln-g102-1183 nx5032ga ln-g102-1182 nx5032ga exs00a-01654 nx5032ga frequency 17.5814 24.19066 24.16139 mhz load capacitance 8 8 8 pf esr 25 15 <70 seb sclk confb (input) mosi (input) miso (output) 9.10 9.8 9.3 9.9 9.2 9.7 9.4 9.5 seb sclk confb (input) mosi (output) 9.6 9.3
MC33596 data sheet, rev. 3 application schematics freescale semiconductor 50 19 application schematics figure 43. MC33596 application schematic (5 v) 19.1 pcb design recommendations pay attention to the following poi nts and recommendations when designing the layout of the pcb. ? ground plane ? if you can afford a multilayer pcb, use an in ternal layer for the ground plane, route power supply and digital signals on the last layer, rf components being located on the first layer. ? use at least a double-sided pcb. ? use a large ground plane on the opposite layer. ? if the ground plane must be cut on the opposit e layer for routing some signals, maintain continuity with another ground plane on the opposite layer and a lot of via to minimize vcc2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 rssiout vcc2rf rfin gndlna v cc2vco gnd nc gnd gnd switch vcc2in gndsubd strobe nc vccin gndio seb sclk mosi miso confb dataclk rssic gnddig xtalin xtal0ut v cc inout vcc2out vccdig vccdig2 rbgap gnd x1 c35 c29 c31 c30 r13 c24 switch c7 vcc2 c3 1 nf c8 rssiout strobe 5 v gnd seb sclk mosi miso confb dataclk rssic vcc2 c22 c20 c6 c40 c39 l7 j1 u14 MC33596 sna vert vcc2
application schematics MC33596 data sheet, rev. 3 freescale semiconductor 51 parasitic inductance. ? power supply, ground connection and decoupling ? connect each ground pin to the ground plane using a separate via for eac h signal; do not use common vias. ? place each decoupling cap acitor as close to the correspondi ng vcc pin as possible (no more than 2?3 mm away). ? locate the vccdig2 decoupling capacitor (c13) directly between vccdig2 (pin 14) and gnd (pin 16). ? rf tracks, matching netw ork and other components ? minimize any tracks used for routing rf signals. ? locate crystal x1 and associated capacitors c15 and c11 close to the MC33596. avoid loops occurring due to component size and tracks. avoid routing digital signals in this area. ? use high frequency coils with high q values fo r the frequency of opera tion (minimum of 15). validate any change of coil source. note the values indicated for the matching network have been computed and tuned for the the MC33596 rf modul es available for MC33596 evaluation. matching networks should be retuned if any change is made to the pcb (track width, length or pl ace, or pcb thickness, or component value). never use, as is, a matching netw ork designed for another pcb.
MC33596 data sheet, rev. 3 case outline dimensions freescale semiconductor 52 20 case outline dimensions 20.1 lqfp32 case
case outline dimensions MC33596 data sheet, rev. 3 freescale semiconductor 53
MC33596 data sheet, rev. 3 case outline dimensions freescale semiconductor 54
case outline dimensions MC33596 data sheet, rev. 3 freescale semiconductor 55 20.2 qfn32 case
MC33596 data sheet, rev. 3 case outline dimensions freescale semiconductor 56
case outline dimensions MC33596 data sheet, rev. 3 freescale semiconductor 57
document number: MC33596 rev. 3 06/2007 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2006, 2007. all rights reserved. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp .

▲Up To Search▲

Price & Availability of MC33596

	To Download MC33596 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .